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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00722 rev. *h revised november 09, 2017 ?spansion, inc.? and ?cypress semiconductor corp.? have merged together to deliver high-performance, high-quality solutions at the heart of today's mo st advanced embedded systems, from automotive, industrial and networ king platforms to highly interactive consumer and mobile devices. the new company ?cypress semiconductor corp.? will continue to offer ?spansion, inc.? products to new and existing customers. continuity of specifications there is no change to this docume nt as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of orde ring part numbers cypress continues to support existing part numbers. to order these products, please use only the ordering part numbers listed i n this document. for more information please visit our website at www.cypress.com or contact your local sales office for additional information about cypress products and services. our customers cypress is for true innovators ? in companies both large and small. our customers are smart, aggressive, out-of-the-box thinkers wh o design and develop game-changing products that revolutionize their industries or create new indu stries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded syst em solutions for the world?s most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypress? s programmable systems-on- chip, general-purpose microcontrollers, analog ics, wireless and usb-based connectivity solutions and reliable, high-performanc e memories help engineers design differentiated products and get them to market first. cypress is committed to providing custom ers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. to learn more, go to www.cypress.com .
S25FL204K 4-mbit 3.0 v spi flash memory cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00722 rev. *h revised november 09, 2017 distinctive features ? single power supply operation ? full voltage range: 2.7 to 3.6v ? 4-mbit serial flash ? 4-mbit/512 kbyte/2048 pages ? 256 bytes per programmable page ? uniform 4-kbyte sectors/64-kbyte blocks ? standard and dual ? standard spi: sck, cs#, si, so, wp#, hold# ? dual spi: sck, cs#, si/io0, so, wp#, hold# ? fast read dual output instruction ? auto-increment read capability ? high performance ? fast read (serial): 85 mhz clock rate ? dual output read: 85 mhz clock rate ? low power consumption ? 12 ma typical active current ? 15 a typical standby current ? flexible architecture with 4 kb sectors ? sector erase (4 kb) ? block erase (64 kb) ? page program up to 256 bytes ? 100k erase/program cycles typical ? 20-year data retention typical ? software and hardware write protection ? write protect all or portion of memory via software ? enable/disable protection with wp# pin ? high performance program/erase speed ? page program time: 1.5 ms typical ? sector erase time (4 kb): 50 ms typical ? block erase time (64 kb): 500 ms typical ? chip erase time: 3.5 seconds typical ? package options ? 8-pin soic 150/208-mil ? all pb-free packages are rohs compliant general description the S25FL204K (4-mbit, 512-kbyte) serial flash memory, with advanced write protection mech anisms. theS25FL204K supports the standard serial peripheral interface (s pi), and a high performance dual output using spi pins: serial clock, chip select, s erial si/io0, so, wp# and hold#. spi clock frequencies of up to 85 mhz are supported along with a clock rate of 85 mhz for dual output read. the S25FL204K array is organized into 2048 programmable pages of 256 bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4 kb sector erase), groups of 256 (64 kb block erase) or the entire chip (chip erase ). the S25FL204K has12 8 erasable sectors and 8 eras able blocks. the small 4 kb sectors allo w for greater flexib ility in applicatio ns that require data and parameter storage. a hold pin, write protect pin and programm able write protection provide further contro l flexibility. additionally, the s25fl204 k device supports jedec standard manufa cturer and device identification.
document number: 002-00722 rev. *h page 3 of 35 S25FL204K table of contents distinctive features ............................................................. 2 general description ............................................................. 2 1. block diagram .............................................................. 4 2. connection diagrams .................................................. 4 3. signal descriptions ..................................................... 5 4. ordering information ................................................... 6 4.1 valid combinations ........................................................ 6 5. memory organizations ................................................ 7 6. functional description ................................................ 8 6.1 spi modes ..................................................................... 8 6.2 dual output spi ............................................................. 8 6.3 hold function................................................................. 8 6.4 status register .............................................................. 9 7. write protection ......................................................... 10 7.1 page programming ...................................................... 11 7.2 sector erase, block erase, and chip erase ................ 11 7.3 polling during a write, program, or erase cycle......... 11 7.4 active power, stand-by power, and deep power-down modes ...... ............................................... 11 8. commands ................................................................. 11 8.1 write enable (06h) ....................................................... 12 8.2 write disable (04h) ...................................................... 13 8.3 read status register (05h) ... .......... ........... ........... ....... 13 8.4 write status register (01h) ........................................... 14 8.5 read data (03h) ..... .............. ........... ........... ........... ....... 15 8.6 fast read (0bh) ..... .............. ........... ........... ........... ....... 15 8.7 fast read dual output (3bh) . ............... .............. ......... 16 8.8 page program (pp) (02h) ............................................. 17 8.9 sector erase (se) (20h)................................................ 18 8.10 block erase (be) (d8h)................................................. 19 8.11 chip erase (ce) (c7h).................................................. 19 8.12 deep power-down (dp) (b9h) ............... .............. ......... 20 8.13 release deep power-down / device id (abh) ............. 21 8.14 read manufacturer / device id (90h) ......... ........... ....... 22 8.15 read identification (rdid) (9 fh) ........... .............. ......... 23 9. electrical specifications ............................................. 25 9.1 power-up timing........................................................... 25 9.2 absolute maximum ratings .... ...................................... 26 9.3 recommended operating ranges ............. ........... ....... 26 9.4 dc characteristics ........................................................ 27 9.5 ac measurement conditions ........................................ 27 9.6 ac characteristics ........................................................ 28 10. package material ......................................................... 31 10.1 8-pin soic 150-mil package (soa 008) ...................... 31 10.2 8-pin soic 208-mil package (soc 008)...................... 32 11. revision history .......................................................... 33
document number: 002-00722 rev. *h page 4 of 35 S25FL204K 1. block diagram 2. connection diagrams address buffers and latches x-decoder flash memory y-decoder control logic i/o buffers and data latches serial interface cs # sck si/io0 so w p# ho ld # 1 2 3 4 cs# so wp# gnd si/io0 sck hold# vcc 5 6 7 8 figure 2.1 8-pin soic (150/208 mil)
document number: 002-00722 rev. *h page 5 of 35 S25FL204K 3. signal descriptions serial data input / output (si/io0) the spi serial data input/output (si/io0) pin provides a means for instructions, addresses and data to be serially written to ( shifted into) the device. data is latched on the rising edge of the serial clock (sck) input pin. the si/io0 pin is also used as an out put pin when the fast read dual output instruction is executed. serial data output (so) the spi serial data output (so) pin provides a means for data and status to be serially read fr om (shifted out of) the device. data is shifted out on the falling edge of the serial clock (sck) input pin. serial clock (sck) the spi serial clock input (sck) pin provides the timing for serial input and output operations. see spi modes on page 8. chip select (cs#) the spi chip select (cs#) pin enables and disables device operat ion. when cs# is high the device is deselected and the serial data output pins are at high impedance. when deselected, the device?s power consumpt ion will be at standby levels unless an inte rnal erase, program or status register cycle is in progress. when cs# is brought low the device will be se lected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up, cs# must transition from high to low before a new instruction will be accepted. hold (hold#) the hold# pin allows the device to be paused while it is active ly selected. when hold# is brought low, while cs# is low, the so pin will be at high impedance and signals on the si and sck pins will be ignored (don?t care). the hold# function can be useful when multiple devices are sharing the same spi signals. write protect (wp#) the write protect (wp#) pin can be used to prevent the status r egister from being written. used in conjunction with the status register?s block protect (bp0, bp1 and bp2, bp3) bits and status register protect (srp) bits, a portion or the entire memory ar ray can be hardware protected. note: 1. si/io0 output is used for dual output read instruction. table 3.1 pin descriptions symbol pin name sck serial clock input si/io0 serial data input / output (1) so serial data output cs# chip enable wp# write protect hold# hold input vcc supply voltage (2.7-3.6v) gnd ground
document number: 002-00722 rev. *h page 6 of 35 S25FL204K 4. ordering information the ordering part number is formed by a valid combination of the following: 4.1 valid combinations table 4.1 lists the valid combinations configurations pl anned to be supported in volume for this device. s25fl 204 k 0t m f i 01 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 04 = 8-pin so package (150 mil) 01 = 8-pin so package (208 mil) temperature range i = industrial (?40c to +85c) package materials f = lead (pb)-free package type m = 8-pin so package speed 0t = 85 mhz device technology k = 0.09 m process technology density 204= 4 mbit device family s25fl spansion memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 4.1 S25FL204K valid combinations S25FL204K valid combinations package marking base ordering part number speed option package and temperature model number packing type S25FL204K 0t mfi 01, 04 0, 1, 3 fl204kif
document number: 002-00722 rev. *h page 7 of 35 S25FL204K 5. memory organizations the memory is organized as: ? 524,288 bytes ? uniform sector architecture ? 8 blocks of 64 kb ? 128 sectors of 4 kb ? 2,048 pages (256 bytes each) each page can be individually programmed (bits are programmed from 1 to 0). the device is sector, block or chip erasable but no t page erasable. figure 5.1 memory organization xxff00h xxffffh .. xxf000h xxf0ffh xxef00h xxefffh .. xxe000h xxe0ffh 07ff00h 07ffffh .. 070000h 0700ffh 06ff00h 06ffffh .. 060000h 0600ffh xx1f00h xx1fffh .. xx1000h xx10ffh xx0f00h xx0fffh 00ff00h 00ffffh .... xx0000h xx00ffh 000000h 0000ffh ? ... sector 15 (4 kb) sector 14 (4 kb) sector 0 (4 kb) sector 1 (4 kb) block 6 (64 kb) block 7 (64 kb) block 0 (64 kb)
document number: 002-00722 rev. *h page 8 of 35 S25FL204K 6. functional description 6.1 spi modes the S25FL204K device can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data i s always available from the falling edge of the sck clock signal. th e difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data. ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 6.1 spi modes 6.2 dual output spi the S25FL204K supports dual output operation when using the ?fast read with dual output? (3b hex) command. this feature allows data to be transferred from the serial flash at twice the rate possible with the standard spi. this command can be used to quickly download code from flash to ram upon power-up (code-s hadowing) or for applications t hat cache code-segments to ram for execution. the dual output feature simply allows the spi data input pin (s i) to also serve as an output during this command. all other operations use the standard spi interface with single signal. the host keeps cs# low and hold# high. the write protect (wp#) signal is ignored. the memory drives data on the si/io0 and so signals during the dual output cycles. the next interface state continues to be dual output cycle until the host returns cs# to high ending the command. 6.3 hold function the hold (hold#) signal is used to pause any serial communicat ions with the S25FL204K device without deselecting the device or stopping the serial clock. to enter the ho ld condition, the device must be selected by driving the cs# input to the logic low s tate. it is recommended that the user keep t he cs# input low state during the entire duration of the hold condition. this is to ensure that the state of the interface logic rema ins unchanged from the moment of entering the hold condition. if the cs# input is driven to th e logic high state while the device is in the hold condition, the inte rface logic of the device will be reset. to restart communication with the device, it is necessary to drive hold# to the logic high state while driving the cs# signal into the logic low state. this prev ents the device from going back into the hold condition. the hold condition starts on the falling edge of the hold (hold#) signal, provided that this coincides with sck being at the lo gic low state. if the falling edge does not coincide with the sck signal bei ng at the logic low state, the hold condition starts whenev er the sck signal reaches the logic low state. taking the hold# signal to the logic low state does not terminate any write, program or erase operation that is currently in progress. cs# mode3 mode 0 mode 3 si/io0 dont care so bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 msb msb high impedance sck mode0
document number: 002-00722 rev. *h page 9 of 35 S25FL204K during the hold condition, so is in high impedance and both t he si and sck input are don't care. the hold condition ends on the rising edge of the hold (hold#) signal, provi ded that this coincides with the sck sign al being at the logic low state. if the r ising edge does not coincide with the sck signal being at the logic lo w state, the hold condition ends whenever the sck signal reache s the logic low state. figure 6.2 hold condition waveform 6.4 status register the status register contains a nu mber of status and control bits that can be read or set (as appropriate) by specific instructi ons ? write in progress (wip) is a read only bit in the status register (r0) which indicates whether the device is performing a program, write, erase operati on, or any other operation, du ring which a new operation command will be ignored. when the wip bit is set to 1, the device is busy performing an operation. when the bit is cleared to 0, no operation is in progress. ? write enable latch (wel) is a read only bit in the status register (r1) th at must be set to 1 to enable program, write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. the write enable (wren) command execution sets the write enable latch to a 1 to allow any program, erase, or write commands to execute afterwards. the write disable (wrdi) command can be used to set the write enable latch to a 0 to prevent all program, erase, and write commands from execution. the wel bit is cleared to 0 at the end of any successful program, write, or erase operation. after a powe r down/power up sequence, hardware reset, or software reset, the write enable latch is set to a 0. ? block protect bits (bp3, bp2, bp1, bp0) are non-volatile read/write bits in the st atus register (r5, r4, r3, and r2) that define the main flash array area to be software protected against program and er ase commands. when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. the chip erase (ce) command can be executed only when the bp bits are cleared to 0?s. see table 7.1 on page 10 for a description of how the bp bit values select the memory array area protected. the factory default setting for all the bp bits is 0, which implies that none of array is protected. ? reserved bits (rev) , status register bit location r6 is reserved for future use. current devices will read 0 for this bit location. it is recommended to mask out the reserved bi t when testing the status register. doing this will ensure compatibility with future devices. ? the status register protect (srp) bit is a non-volatile read/write bit in status register (r7) that can be used in conjunction with the write protect (wp#) pin to disable writes to status r egister. when the srp bit is set to a 0 state (factory default) t he wp# pin has no control over status register. when the srp pin is set to a 1, the write status register instruction is locked out while the wp# pin is low. when the wp# pin is hi gh the write status register instruction is allowed. table 6.1 status register bit locations r7 r6 r5 r4 r3 r2 r1 r0 srp rev bp3 bp2 bp1 bp0 wel wip sck hold# active hold active hold active
document number: 002-00722 rev. *h page 10 of 35 S25FL204K 7. write protection some basic protection against unintended changes to stored data is provided and controlled purely by the hardware design. these protection mechanisms in the S25FL204K device are described below: ? power-on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. ? program, erase and write status register in structions are checked that they consist of a number of clock pulses that is a multiple of eight, before th ey are accepted for execution. ? all instructions that modify data must be preceded by a wr ite enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion or write status register (wrsr) instruction completion or page program (pp) instruction completion or sector erase (se) instruction completion or block erase (b e) instruction completion or chip erase (ce) instruction completion ? the block protect (bp3, bp2, bp1, and bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). ? the write protect (wp#) signal allows the block protect (bp3, bp2, bp1, bp0) bits and status register protect (srp) bit to be protected. this is the ha rdware protected mode (hpm). ? in addition to the low power consumpti on feature, the deep power-down mode of fers extra software protection from inadvertent write, program and erase instructions, as all inst ructions are ignored except one particular instruction (the release from deep power-down instruction). table 7.1 protected area sizes block organization ? S25FL204K status bit protect blocks bp3 bp2 bp1 bp0 0000 0 (none) 0001 1 (1 block, block 7th) 0010 2 (2 blo cks, block 6th~7th) 0011 3 (4 blo cks, block 4th~7th) 0100 4 (8 blocks, all) 0101 5 (8 blocks, all) 0110 6 (8 blocks, all) 0111 7 (8 blocks, all) 1000 8 none 1001 9 (126 sectors, sector 0th~125th) 1010 10 ( 124 sectors, sector 0th~123rd) 1011 11 (120 sectors, sector 0th~119th) 1100 12 (112 sectors, sector 0th~111th) 1101 13 (96 sectors, sectors 0th~95th) 1110 14 (64 sectors, sectors 0th~63rd) 1111 15 (128 sectors, all)
document number: 002-00722 rev. *h page 11 of 35 S25FL204K 7.1 page programming to program one data byte, two instructions are required: write enable (wren), whic h is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal progra m cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 byte s to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. 7.2 sector erase, block erase, and chip erase the page program (pp) instruction allows bi ts to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved a sector at a time, using the sector erase (se) instruction, a block at a tim e using the block erase (be) instruction or throughout the entire memory, using the chip erase (ce) instru ction. this starts an interna l erase cycle (of duration t se, t be, or t ce ). the erase instruction must be preceded by a write enable (wren) instruction. 7.3 polling during a write, program, or erase cycle a further improvement in the time to write status register (wrsr) , program (pp) or erase (se, be, or ce) can be achieved by not waiting for the worst case delay (t w , t pp , t se , t be , or t ce ). the write in progress (wip) bit is prov ided in the status register so that the application program can monitor its value, polling it to es tablish when the previous write cycle, program cycle or erase cy cle is complete. 7.4 active power, stand-by power, and deep power-down modes when chip select (cs#) is low, the device is enabled, and in th e active power mode. when chip select (cs#) is high, the device is disabled, but could remain in the acti ve power mode until all internal cycles have completed (program, erase, write status register). the device then goes into the standby power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when t he specific instruction (the enter deep power-down mode (dp) instruction) is executed with the devic e consumption at i cc2 . the device remains in this mode until anot her specific instruction (the release from deep power-down mode and read device id (rdi) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. 8. commands the command set of the S25FL204K consists of fifteen basic in structions that are fully controlled through the spi bus (see table 8.1 ). the host system must shift all comma nds, addresses, and data in and ou t of the device, begi nning with the most significant bit. on the first rising edge of sck after cs# is driven low, the device accepts t he one-byte command on si (all commands are one byte long), most significant bit first. each successive bit is latched on the rising edge of sck. every command sequence begins with a one-byte command code . the command may be followed by address, data, both, or nothing, depending on the command. cs# must be driven high afte r the last bit of the command sequence has been written. all commands that write, program or erase requ ire that cs# be driven high at a byte b oundary, otherwise the command is not executed . since a byte is composed of eight bits, cs# must therefore be dr iven high when the number of clock pulses after cs# is driven l ow is an exact multiple of eight. the device ignores any attempt to access the memory array during a write registers, program, or erase operation, and continues the operation uninterrupted. table 8.1 command set command name byte1 code byte2 byte3 byte4 byte5 byte6 n-bytes write enable 06h write disable 04h read status register 05h (s7-s0) (1) (note 2)
document number: 002-00722 rev. *h page 12 of 35 S25FL204K notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ?( )? indicate data being read f rom the device on the so pin. 2. the status register contents will repeat continuously until cs# terminates the instruction. 3. see table 8.2, manufacturer and device identification on page 12 for device id information. 4. the device id will repeat continuously until cs# terminates the instruction. 8.1 write enable (06h) the write enable command ( figure 8.1 ) sets the write enable latch (wel) bit in the status register to a 1, which enables the device to accept a write status register, program, or erase command. the wel bit must be set prior to every page program, sector erase, block erase, chip erase, and write status r egister command. the host system must first drive cs# low, wr ite the wren command, and then drive cs# high. write status register 01h s7-s0 read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) continuous fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) (next byte) continuous fast read dual output 3bh a23-a16 a15-a8 a7-a0 dummy i/o= (d6, d4, d2, d0) o= (d7, d5, d3, d1) (one byte per 4 clocks, continuous) page program 02h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) up to 256 bytes block erase (64 kb) d8h a23-a16 a15-a8 a7-a0 sector erase (4 kb) 20h a23-a16 a15-a8 a7-a0 chip erase c7h/60h power-down b9h release power-down / device id abh dummy dummy dummy (id7-id0) (4) manufacturer / device id (3) 90h dummy dummy 00h (m7-m0) (id7-id0) jedec id 9fh (m7-m0) manufacturer (id15-id8) memory type (id7-id0) capacity table 8.2 manufacturer and device identification op code (m7-m0) (id15-id0) (id7-id0) abh 12h 90h 01h 12h 9fh 01h 4013h table 8.1 command set command name byte1 code byte2 byte3 byte4 byte5 byte6 n-bytes
document number: 002-00722 rev. *h page 13 of 35 S25FL204K figure 8.1 write enable command sequence 8.2 write disable (04h) the write disable command ( figure 8.2 ) resets the write enable latch (wel) bit to a 0, which disables the device from accepting a write, program or erase command. the host system must first dr ive cs# low, write the wrdi co mmand, and then drive cs# high. the wel bit is automatically reset after power-up and upon comple tion of the write status regi ster, page program, sector erase, block erase, and chip erase commands. figure 8.2 write disable command sequence 8.3 read status register (05h) the read status register (rdsr) command outputs the state of the status register bits. the rdsr command may be written at any time, even while a program, erase, or write registers operation is in progress. the host system should check the write in progress (wip) bit before sending a new command to the device if an operation is already in progress. figure 8.3 shows the rdsr command sequence, which also shows that it is possible to read the status register continuously until cs# is driven high. (see section 6.4, status register on page 9 ). cs sck 05 4 3 1 2 7 6 mode0 mode0 mode3 mode3 si/io0 so high impedance instruction(06h) cs sck 05 4 3 1 2 7 6 mode0 mode0 mode3 mode3 si/io0 so high impedance instruction(04h)
document number: 002-00722 rev. *h page 14 of 35 S25FL204K figure 8.3 read status register command sequence 8.4 write status register (01h) the write status register command allows the status register to be written. a write enable command must previously have been executed for the device to accept the writ e status register command (status register bit wel must equal 1). once write enabled, the command is entered by driving cs# low, sending the instruction code ?01h?, and then writing the status register data byte a s illustrated in figure 8.4 . the status register bits are shown in table 6.1 on page 9 and described in section 6.4, status register on page 9 . only non-volatile status register bits srp, bp3, bp2, bp1, and bp0 (bits 7, 5, 4, 3, and 2) c an be written to. all other status register bit locations are read-only and will not be affected by the write st atus register command. the cs# chip select input pin must be driven to the logic hi gh state after the eighth bit of data has been latched in. if not, the write status register command is not executed. as soon as the cs# chip select input pin is driven to the logic high state, the self-t imed write status register cycle is initiated. while the write status register cycle is in progress, the status register may still b e read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is a 1 during the self-timed write status r egister cycle, and is a 0 when it is completed. when the write status regi ster cycle is completed, the write enable latch (wel) is set to a 0. the write status register command allows the block protect bits (bp3, bp2, bp1, and bp0) to be set for protecting all, a portio n, or none of the memory from erase and program co mmands. protected areas become read-only (see table 7.1 on page 10 ). the write status register command also allows the st atus register protect bit (srp) to be set. th is bit is used in conjunction with the w rite protect (wp#) pin to disable writes to the status register. when the srp bit is set to a 0 state (factory default) the wp# pin has no control over the status register. when the srp pin is set to a 1, the write status register co mmand is locked out while the wp# pin is low. when the wp# pin is high the writ e status register command is allowed. cs# sck mode0 mode3 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 21 20 19 18 17 16 23 22 si/io0 instruction (05h) so *=m sb status register out status register out * * high impedance 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
document number: 002-00722 rev. *h page 15 of 35 S25FL204K figure 8.4 write status register command sequence 8.5 read data (03h) the read data command allows one more data bytes to be sequenti ally read from the memory. the command is initiated by driving the cs# pin low and then shifting the instruct ion code ?03h? followed by a 24-bit address (a23-a0) into the si/io0 pin. the cod e and address bits are latched on the rising edge of the sck pin. afte r the address is received, the data byte of the addressed memor y location will be shifted out on the so pin at the falling edge of sck with most significant bit (msb) first. the address is aut omatically incremented to the next higher address after ea ch byte of data is shifted out allowing fo r a continuous stream of data. this me ans that the entire memory can be accessed with a single command as long as the clock continues. the command is completed by driving cs# high. the read data command sequence is shown in figure 8.5 . if a read data command is issued while an erase, program or write cycle is in process (wip=1) the command is ignored and will not have any effects on the current cycle. the read data command allows clock rates from d.c. to a maximum of f r . see ac characteristics on page 28. figure 8.5 read data command sequence 8.6 fast read (0bh) the fast read command is similar to the read data command except that it can operate at higher frequency than the traditional read data command. see ac characteristics on page 28. this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 8.6 . the dummy clocks allow t he device?s internal circuits additi onal time for setting up the initial address. during the dummy clocks the data value on the si pin is a ?don?t care?. cs# sck mode0 mode3 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 mode3 mode0 si/io0 instruction(01h) so high impedance * *= m sb 7 6 5 4 3 2 1 0 cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 39 38 37 36 35 34 33 32 31 28 29 si/io0 instruction (03h) so high impedance 23 2 3 21 22 0 1 6 7 5 2 3 1 4 0 * * *=m sb 24-bit address data o ut 1 data o ut 2 7
document number: 002-00722 rev. *h page 16 of 35 S25FL204K figure 8.6 fast read command sequence 8.7 fast read dual output (3bh) the fast read dual output (3bh) command is similar to the standar d fast read (0bh) command except that data is output on two pins, so and si/io0, instead of just so. this allows data to be transferred from the S25FL204K at twice the rate of standard sp i devices. the fast read dual output comma nd is ideal for quickly downloading code from the spi flash to ram upon power-up or for applications that cache code-segments to ram for execution. similar to the fast read command, the fast read dual output command can operate at higher frequencies than the traditional read data command. see ac characteristics on page 28. this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 8.7 . the dummy clocks allow t he device's internal circ uits additional time fo r setting up the initial address. the input data during the dummy cloc ks is ?don?t care?. however, the si/io0 pin should be high-impedance prior to the falling edge of the first data out clock. cs# sck 32 33 42 41 40 39 38 37 36 35 34 45 54 53 51 51 50 49 48 47 46 43 44 si/io0 dummy clocks 6 7 5 2 3 1 4 0 * *=m sb data o ut 1 7 cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (0bh) so high impedance 23 2 3 21 22 0 1 * 24-bit address 6 7 5 2 3 1 40 * 6 7 5 2 3 1 4 0 data o ut 1 55 * so
document number: 002-00722 rev. *h page 17 of 35 S25FL204K figure 8.7 fast read dual output command sequence 8.8 page program (pp) (02h) the page program command allows up to 256 bytes of data to be programmed at previously erased to all 1s (ffh) memory locations. a write enable command must be executed before the device will accept the page progr am command (status register bit wel must equal 1). the command is initia ted by driving the cs# pin low then shifting the command code ?02h? followed by a 2 4- bit address (a23-a0) and at least one data byte, into the si/io0 pin. the cs# pin must be held low for the entire length of the command while data is being sent to the device. the page program command sequence is shown in figure 8.8 . if an entire 256 byte page is to be programmed, the last addre ss byte (the 8 least significant address bits) should be set to 0 . if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the begin ning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without havi ng any effect on other bytes wit hin the same page. one condition to perform a partial page program is that the number of clocks can not exce ed the remaining page length. if more than 256 bytes ar e sent to the device the addressing will wrap to the beginning of the page and overwrite previ ously sent data. as with the write and erase commands, the cs# pin must be driven high after the eight h bit of the last byte has been latched. i f this is not done the page program command will not be executed. after cs# is driven high, the self-timed page program command will commence for a time duration of t pp . see ac characteristics on page 28. while the page program cycle is in progress, the read status register command may still be accessed for checking the st atus of the wip bit. the wip bi t is a 1 during the page progra m cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page program command will not b e executed if the addressed page is protected by the block protect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 10 ). cs# sck 32 33 42 41 40 39 38 37 36 35 34 45 54 53 51 51 50 49 48 47 46 43 44 si/io0 dummy clocks so 5 7 3 5 7 3 1 1 * *=m sb 7 cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (3bh) so high impedance 23 2 3 21 22 0 1 * 24-bit address 5 7 3 5 7 3 11 * 55 * 4 6 2 4 6 2 0 0 4 6 2 4 6 2 0 0 6 * * si/io0 switches from input to output d ata out 1 d ata out 2 d ata out 3 d ata out 4
document number: 002-00722 rev. *h page 18 of 35 S25FL204K figure 8.8 page program command sequence 8.9 sector erase (se) (20h) the sector erase command sets all bits in the addressed 4 kb sector to 1 (all bytes are ffh). before the sector erase command c an be accepted by the device, a write enable command must be issued and decoded by the device, which sets the write enable latch bit in the status register to enable any write operations. the command is initiated by driving the cs# pin low and shifting the command code ?20h? followed by a 24-bit sector address (a 23-a0). the sector erase command sequence is shown in figure 8.9 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase co mmand will not be executed. after cs# is driven high, the self-timed sector erase command will commence for a time duration of t se . see ac characteristics on page 28. while the sector erase cycle is in progress, the read status register command may still be accessed for checking the status of the wip bit. the wip bit is a 1 du ring the sector erase cycle an d becomes a 0 when the cycl e is finished and the device is ready to accept other commands aga in. after the sector erase cycle has finished the write enable lat ch (wel) bit in the status register is cleared to 0. the sector erase command will not be executed if the addressed page is protec ted by the block protect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 10 ). cs# sck 40 41 50 49 48 47 46 45 44 43 41 53 2072 55 54 51 52 si/io0 data byte 2 so 6 7 5 2 3 1 40 * *=m sb data byte 256 cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (02h) so high impedance 23 2 3 21 22 0 1 * 24-bit address 6 7 5 2 3 1 40 * 6 7 5 2 3 1 4 0 data byte 3 34 35 32 33 38 39 37 36 6 7 5 2 3 1 4 0 * 2078 2077 2076 2075 2074 2073 2079 mode0 mode3 * data byte 1 high impedance
document number: 002-00722 rev. *h page 19 of 35 S25FL204K figure 8.9 sector erase command sequence 8.10 block erase (be) (d8h) the block erase command sets all bits in the addressed 64 kb block to 1 (all bytes are ffh). before the be command can be accepted by the device, a write enable comm and must be issued and decoded by the devi ce, which sets the write enable latch in the status register to enable any write operations. the command is initiated by driving the cs# pin low and shifting the comman d code ?d8h? followed a 24-bit block address (a23-a0). the block erase command sequence is shown in figure 8.10 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase com mand will not be executed. after cs# is driven high, the self-timed block erase command will commence for a time duration of t be . see ac characteristics on page 28. while the block erase cycle is in progress, the r ead status register comm and may still be accessed for checking the status of the wip bit. t he wip bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finis hed and the device is ready to accept other commands again. after the block erase cycle ha s finished the write enable latch (wel) b it in the status register is cleared to 0. the block erase command will not be executed if the addr essed page is protected by the block protect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 10 ). figure 8.10 block erase command sequence 8.11 chip erase (ce) (c7h) the chip erase command sets all bits to 1 (all bytes are ffh) inside the entire flash memory array. before the ce command can b e accepted by the device, a write enable comm and must be issued and decoded by the devi ce, which sets the write enable latch in the status register to enable any write operations. the command is initiated by driving the cs# pin low and shifting the comman d code ?c7h?. the chip erase command sequence is shown in figure 8.11 . cs# sck mode0 mode3 01 31 30 29 9 8 7 6 5 4 3 2 mode3 mode0 si/io0 instruction(20h) so high impedance * *=m sb 23 22 2 1 0 24-bit address cs# sck mode 0 mode 3 01 31 30 29 9 8 7 6 5 4 3 2 mode3 mode0 si/io0 in stru ctio n (d8) so high impedance * *=m sb 23 22 2 1 0 24-bit address
document number: 002-00722 rev. *h page 20 of 35 S25FL204K the cs# pin must be driven high after the eighth bit has been latc hed. if this is not done the chip erase command will not be executed. after cs# is driven high, the self-timed chip erase command will commence for a time duration of t ce . see ac characteristics on page 28. while the chip erase cycle is in progress, the read status register command may still be accessed to check the status of the wip bit. the wip bit is a 1 dur ing the chip erase cycle and becomes a 0 when finished and the device is ready to accept other commands a gain. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase command will not be ex ecuted if any page is protected by the block protect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 10 ). figure 8.11 chip erase command sequence 8.12 deep power-down (dp) (b9h) the deep power-down (dp) command provides the lowest power c onsumption mode of the device. it is intended for periods when the device is not in active use, and ignores all commands e xcept for the release from deep power-down (res) command. the lower power consumption makes the deep power-down command espe cially useful for battery powered applications (see i cc1 and i cc2 in dc characteristics on page 27 .) the command is initiated by driving the cs # pin low and shifting the command code ?b9h? as shown in figure 8.12 . the cs# pin must be driven high after the eighth bit has been la tched. if this is not done the deep power-down command will not be executed. after cs# is driven high, the power-down state will enter within t he time duration of t dp ( see ac characteristics on page 28. ) while in the power-down state only the release from power-down / device id command, which restores the device to normal operation, will be recognized. all other commands are ignor ed. this includes the read status register command, which is always available during normal operation. the deep power-down m ode therefore provides the maximum data protection against unintended write operations. deep power- down mode automatically terminates when po wer is removed, and the device always powers up in the standard standby mode. the device rejects any deep power-down command issued while it is executing a program, erase, or write registers operatio n, and continues the operation uninterrupted. cs# sck 05 4 3 1 2 7 6 mode0 mode0 mode3 mode3 si/io0 so high impedance instruction(c7h)
document number: 002-00722 rev. *h page 21 of 35 S25FL204K figure 8.12 deep power-down command sequence 8.13 release deep power-do wn / device id (abh) the release from deep power-down / device id command is a multi-purpose command. the device requires the release from deep power-down command to exit the deep power-down mode. wh en the device is in the deep power-down mode, all commands except release from deep power-down command are ignored. in addition, the abh command can also be used to read the device's 8-bit electronic device id. when used only to release the device from the power-down state, the command is issued by driving the cs# pin low, shifting the command code ?abh? and driving cs# high as shown in figure 8.13 . after the time duration of t res1 ( see ac characteristics on page 28. ) the device will resume normal operation and other comm ands will be accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the deep power-down state, the command is initiated by driving the cs# pin low and shifting the command code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of s ck with most significant bit (msb) first as shown in figure 8.14 . the device id value for the S25FL204K is listed in manufacturer and device identification table. the device id can be read c ontinuously. the command is co mpleted by driving cs# high. when used to release the device from the deep power-down st ate and obtain the device id, the command is the same as previously described, and shown in figure 8.14 , except that after cs# is driven high it must remain high for a time duration of t res2 ( see ac characteristics on page 28. ). after this time duration the device will re sume normal operation and other commands will be accepted. if the release from deep power-down / device id comm and is issued while an erase, program or write cycle is in process (when wip equals 1) the command is ignored and will not have any effects on the current cycle. figure 8.13 release deep power-down command cs# sck 05 4 3 1 2 7 6 mode0 mode3 si/io0 so high impedance instruction(b9h) mode3 t dp standard current power-down current mode0 cs# sck 05 4 3 1 2 7 6 mode0 mode3 si/io0 so high impedance instruction(abh) mode3 t res1 deep p o w e r-d o w n c u rre n t high performance current stand-by current mode0
document number: 002-00722 rev. *h page 22 of 35 S25FL204K figure 8.14 release deep power-down / device id command sequence 8.14 read manufacturer / device id (90h) the read manufacturer/device id command is an alternative to the release from deep power-down /device id command that provides both the jedec assigned manufac turer id and the specific device id. the read manufacturer/device id command is very similar to the release from deep power-down / device id command. the command is initiated by driving the cs# pin low and shifting t he command code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id for spansion (01h) and the device id are shifted out on the falling edge of sck with most significant bit (msb) first as shown in figure 8.15 . the device id values for the S25FL204K are listed in table 8.2 on page 12 . if the 24-bit address is initially set to 000001h the device id will be read first, followed by the manufacturer id. *=m sb cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (abh ) so high impedance 23 2 3 21 22 0 1 * 3 dummy bytes 34 35 32 33 38 37 36 6 7 5 2 3 1 4 0 * mode3 mode0 device id ** t res2 power down current high performance mode current stand-by current
document number: 002-00722 rev. *h page 23 of 35 S25FL204K figure 8.15 read manufacturer / device id command sequence 8.15 read identification (rdid) (9fh) for compatibility reasons, the S25FL204K provides several commands to electronically determine the identity of the device. the read jedec id command is compatible with the jedec standard fo r spi compatible serial memories that was adopted in 2003. the command is initiated by driving the cs# pin low and shifting the command code ?9 fh?. the jedec assigned manufacturer id byte for spansion (01h) and two device id bytes, memory type (id 15-id8) and capacity (id7-id0) ar e then shifted out on the fall ing edge of sck with most significant bit (msb) first as shown in figure 8.16 . for memory type and capacity values refer to table 8.2, manufacturer and device identification on page 12 . cs# sck 32 33 42 41 40 39 38 37 36 35 34 45 46 43 44 si/io0 62 *=msb cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (90h) so high impedance 23 2 3 21 22 0 1 * address ? 000000 h ? 6 7 5 2 3 1 40 * * manufacturer id device id** mode0 mode3
document number: 002-00722 rev. *h page 24 of 35 S25FL204K figure 8.16 read jedec id command sequence cs# sck mode0 mode3 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 si/io0 instruction (9fh) so manufacturer id * high impedance cs# sck 16 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 mode3 mode0 si/io0 memory type id 15-id8 so * *=m sb 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 c apacity id 7-id 0 *
document number: 002-00722 rev. *h page 25 of 35 S25FL204K 9. electrical specifications 9.1 power-up timing figure 9.1 power-up timing notes: 1. the parameters are characterized only. 2. v cc (max.) is 3.6v and v cc (min.) is 2.7v. table 9.1 power-up voltage and timing parameter symbol type unit min max v cc (min) to cs# low t vsl (1) 10 s time delay before write instruction t puw (1) 110ms write inhibit threshold voltage v wi (1) 12v vcc (max) vcc (min) v wi reset stast t vsl cs# must track vcc program, e rase, and write instruction are ignored read instructions allowed device is fully accessible t puw vcc time
document number: 002-00722 rev. *h page 26 of 35 S25FL204K 9.2 absolute maximum ratings stresses above the values so mentioned above may cause permanen t damage to the device. these values are for a stress rating only and do not imply that the device should be o perated at conditions up to or above these values. notes: 1. specification for S25FL204K is advance information. 2. this device has been designed and tested for the specified oper ation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 3. compliant with jedec standard j-std-20c for small body sn-pb or pb-free (green) assembly and the european directive on restri ctions on hazardous substances (rohs) 2002/95/eu. 9.3 recommended operating ranges note: 1. recommended operating ranges define those limits betwee n which the functionality of the device is guaranteed. table 9.2 absolute maximum ratings parameters symbol conditions range unit supply voltage v cc -0.6 to +4.0 v voltage applied on any pin v io relative to ground -0.6 to v cc +0.4 v transient voltage on any pin v iot <20 ns transient relative to ground -2.0 to v cc +2.0 v storage temperature t stg -65 to +150 c lead temperature t lead (note 3) c table 9.3 recommended operating ranges parameter symbol conditions spec unit min max supply voltage v cc f r = 85 mhz, f r = 44 mhz 2.7 3.6 v ambient temperature, operating t a industrial -40 +85 c
document number: 002-00722 rev. *h page 27 of 35 S25FL204K 9.4 dc characteristics this section summarizes the dc characteristics of the device. de signers should check that the operating conditions in their cir cuit match the measurement conditions specifi ed in the ac measurement conditions in table 9.6 on page 28 , when relying on the quoted parameters. notes: 1. tested on sample basis and specified through design and characterization data. t a =25c, v cc 3v. 2. checker board pattern. 9.5 ac measurement conditions table 9.4 dc characteristics symbol (notes) parameter (notes) conditions (notes) spec unit min typ max c in (1) input capacitance v in = 0v (2) 6pf c out (1) output capacitance v out = 0v (2) 8pf i li input leakage 2 a i lo i/o leakage 2 a i cc1 standby current cs# = v cc , v in = gnd or v cc 15 35 a i cc2 power-down current cs# = v cc , v in = gnd or v cc 15 32 a i cc3 current read data / dual output read 33 mhz (2) c = 0.1 v cc / 0.9 v cc do = open 10/12 15/18 ma i cc3 current read data / dual output read 100 mhz (2) c = 0.1 v cc / 0.9 v cc so = open 25 ma i cc4 current page program cs# = v cc 15 20 ma i cc5 current write status register cs# = v cc 10 18 ma i cc6 current sector/block erase cs# = v cc 20 25 ma i cc7 current chip erase cs# = v cc 20 25 ma v il input low voltage -0.5 vcc x 0.3 v v ih input high voltage v cc x0.7 v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -100 a v cc -0.2 v table 9.5 ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf t r , t f input rise and fall times 5 ns v in input pulse voltages 0.2 v cc to 0.8 v cc v vtin input timing reference voltages 0.3 v cc to 0.7 v cc v vton output timing reference voltages 0.5 v cc to 0.5 v cc v
document number: 002-00722 rev. *h page 28 of 35 S25FL204K figure 9.2 ac measurement i/o waveform 9.6 ac characteristics table 9.6 ac characteristics (sheet 1 of 2) symbol (notes) alt parameter (notes) spec unit min typ max f r f c clock frequency for all instructions, except read data (03h) and dual output (3bh) d.c. 85 mhz clock frequency for dual output (3bh) 85 mhz f r clock freq. read data instruction (03h) d.c. 44 mhz t clh , t cll (1) clock high, low time for all instructions except read data (03h) 4ns t crlh , t crll (1) clock high, low time for read data (03h) instruction 4ns t clch (2) clock rise time peak to peak 0.1 v/ns t chcl (2) clock fall time peak to peak 0.1 v/ns t slch t css cs# active setup time relative to sck 6 ns t chsl cs# not active hold time relative to sck 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh cs# active hold time relative to sck 5 ns t shch cs# not active setup time relative to sck 5 ns t shsl t csh cs# deselect time (for array read 'array read / erase or program ' read status register) 50/100 ns t shqz (2) t dis output disable time 6 ns t clqv t v clock low to output valid 10 ns t clqx t ho output hold time 0 ns t hlch hold# active setup time relative to sck 5 ns t chhh hold# active hold time relative to sck 5 ns t hhch hold# not active setup time relative to sck 5 ns t chhl hold# not active hold time relative to sck 5 ns t hhqx (2) t lz hold# to output low-z 7 ns t hlqz (2) t hz hold# to output high-z 12 ns t whsl (3) write protect setup time before cs# low 20 ns t shwl (3) write protect hold time after cs# high 100 ns t dp (2) cs# high to power-down mode 3 s t res1 (2) cs# high to standby mode without electronic signature read 3s input levels 0.8 vcc 0.2 vcc 0.3 vcc 0.7 vcc input and output timing reference levels
document number: 002-00722 rev. *h page 29 of 35 S25FL204K notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characte rization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when sector protect bit is set to 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. max value shown is for less than 10k cycles. for greater than 10k cycles, max value is 5.3s. 6. max value shown is for less than 10k cycles. for greater than 10k cycles, max value is 8.4s. figure 9.3 serial output timing figure 9.4 input timing t res2 (2) cs# high to standby mode with electronic signature read 1.8 s t w write status register time 10 15 ms t bp1 byte program time (first byte) (4) 30 50 s t bp2 additional byte program time (after first byte) (4) 612s t pp page program time 1.5 5 ms t se sector erase time (4 kb) 50 300 ms t be (5) block erase time (64 kb) 0.5 2 s t ce (6) chip erase time 3.5 7 s table 9.6 ac characteristics (sheet 2 of 2) symbol (notes) alt parameter (notes) spec unit min typ max cs# sck so / si(io0) (note) lsb out t clqx t clqv t clqx t clqv t cl t ch t clql t clqh t shqz note: si(io0) is an o utput o nly for the fast read dual output command (3bh) cs# sck t chsl t slch t clch tshsl t shch t chsh t chcl si/io0 t dvch t chdx msb in lsb in so high impedance
document number: 002-00722 rev. *h page 30 of 35 S25FL204K figure 9.5 hold timing cs# sck si/io0 t hlqz t chhl so t hlch hold# thhch t hhq h t chhh
document number: 002-00722 rev. *h page 31 of 35 S25FL204K 10. package material 10.1 8-pin soic 150-mi l package (soa 008) g1019 \ 16-038.3f \ 10.06.11 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane.
document number: 002-00722 rev. *h page 32 of 35 S25FL204K 10.2 8-pin soic 208-mi l package (soc 008) 3602 \ 16-038.03 \ 9.1.6 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane. package soc 008 (inches) soc 008 (mm) jedec symbol min max min max a 0.069 0.085 1.753 2.159 a1 0.002 0.0098 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0.356 0.483 b1 0.013 0.018 0.330 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.008 0.152 0.203 d 0.208 bsc 5.283 bsc e 0.315 bsc 8.001 bsc e1 0.208 bsc 5.283 bsc e .050 bsc 1.27 bsc l 0.020 0.030 0.508 0.762 l1 .049 ref 1.25 ref l2 .010 bsc 0.25 bsc n 8 8 0? 8? 0? 8? 1 5? 15? 5? 15? 2 0? 0?
document number: 002-00722 rev. *h page 33 of 35 S25FL204K 11. revision history spansion publication number: S25FL204K_00 section description revision 01 (november 2, 2011) initial release revision 02 (december 21, 2011) dc characteristics updated i cc2 values revision 03 (january 6, 2012) distinctive features updated standby current value revision 04 (june 8, 2012) global changed data sheet designat ion to ?preliminary? changed f r to 86 mhz recommended operating ranges table changed supply voltage frequency dc characteristics table updated i cc1 and i cc2 values ac characteristics table modified f r , f r , and t clqv revision 05 (august 14, 2012) status register changed status regist er bit r0 from ?busy? to ?wip? global changed ?busy? to ?wip? ac characteristics ac characteristics table: changed f r max value from 86 to 85 changed t slch min value from 5 to 6 added note 5 and note 6 revision 06 (january 17, 2013) cover sheet added nantronics logo to cover sheet revision 07 (september 16, 2013) global changed data sheet designation to ?full production?
document number: 002-00722 rev. *h page 34 of 35 S25FL204K document history document title: S25FL204K 4-mbit 3.0 v spi flash memory document number: 002-00722 rev. ecn no. orig. of change submission date description of change ** ? bwha 11/02/2011 initial release *a ? bwha 12/21/2011 updated i cc2 values *b ? bwha 01/06/2012 updated standby current value *c ? bwha 06/08/2012 changed data sheet designation to ?preliminary? changed f r to 86 mhz changed supply voltage frequency updated i cc1 and i cc2 values modified f r , f r , and t clqv *d ? bwha 08/14/2012 changed status register bit r0 from ?busy? to ?wip? changed ?busy? to ?wip? ac characteristics table: changed fr max value from 86 to 85 changed t slch min value from 5 to 6 added note 5 and note 6 *e ? bwha 01/17/2013 added nantronics logo to cover sheet *f ? bwha 09/16/2013 changed data sheet designation to ?full production? *g 4926108 aspa 09/18/2015 updated to cypress template *h 5962322 aesatmp8 11/ 09/2017 updated logo and copyright.
document number: 002-00722 rev. *h revised november 09, 2017 page 35 of 35 ? cypress semiconductor corporation, 2011-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. 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